This invention relates in general to memory arrays and, more particularly, to a method and apparatus for reducing leakage current in an SRAM array.
Modern electronic equipment, such as televisions, telephones, radios, and computers are generally constructed of solid state devices. Solid state devices include transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers, and other components of an integrated circuit. One type of memory array is a static random access memory (SRAM) in which memory cells are continuously available for reading and writing data. As technology improves, SRAM cells and other components are fabricated at smaller sizes and with greater on-chip integration.
The increasing level of on-chip integration has allowed steady improvements in modern microprocessor performance, but has also resulted in high energy dissipation in integrated circuits. In complementary metal-oxide-silicone (CMOS) circuits, high transistor-switching speeds can be achieved by reducing the supply voltage, which proportionately reduces the transistor threshold voltage. However, decreasing the transistor threshold voltage may increase the amount of xe2x80x9cstaticxe2x80x9d or xe2x80x9cleakagexe2x80x9d power dissipated by the CMOS circuit. As transistor threshold voltages continue to be reduced in emerging technologies, leakage power is becoming a sizable percentage of the total power consumed in CMOS circuits.
In accordance with the present invention, a method and apparatus for reducing leakage current in an SRAM array are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed methods and apparatuses.
According to one embodiment, a memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row includes a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor includes a first active region. The strap cell row includes a strap cell that includes a first strap cell body region. The first strap cell body region is conductively coupled to the first bit cell body region. The first power supply line is electrically coupled to the first active region and provides a first supply voltage potential to the first active region. The first offset supply line is electrically coupled to the first strap cell body region and provides a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.
According to another embodiment, a method of reducing memory array leakage current is provided. The method includes providing a memory array including a bit cell and a strap cell. The bit cell includes a first transistor disposed in a first bit cell body region. The first transistor includes a first active region. The strap cell includes a first strap cell body region that is conductively coupled to the first bit cell body region. The method further includes applying a first supply voltage potential to the first active region. The method further includes applying a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.
Various embodiments of the present invention may benefit from numerous technical advantages. It should be noted that one or more embodiments may benefit from some, none, or all of the advantages discussed below.
One technical advantage of the invention is that leakage current in a memory array may be reduced by increasing the low power supply voltage applied to the source of a transistor in the memory cell with respect to a substrate supply voltage applied to the substrate of the memory cell, and/or decreasing the high power supply voltage applied to the source of another transistor in the memory cell with respect to an n-well supply voltage applied to the n-well of the memory cell. In particular, the low and high power supply voltages may be maintained or controlled separately from the substrate and n-well supply voltages, respectively.
Another technical advantage is that the low and high power supply voltages applied to the memory array may be maintained or controlled separately from the low and high power supply voltages applied to a peripheral circuit, such as a logic circuit.
Another technical advantage is that one or more of the voltages applied to the memory array may be controlled during different modes of the memory array or particular bit cells, including a standby mode and an active mode, in order to control or to maximize the reduction of leakage current in the memory array.
Another technical advantage is that a strap cell having a structure that substantially mimics or emulates the structure of surrounding bit cells in the memory array may be used to provide the substrate and n-well supply voltages separate from the low and high power supply voltages applied to the memory array. This provides the advantage of more uniform patterning and processing of bit cells adjacent to the strap cell.
Another technical advantage is that the layout of the memory array allows a relatively wide spacing of strap cell rows, which may reduce the cost of including strap cells in a memory array.
Another technical advantage is that the well voltages within the memory array, including for example the n-well and substrate voltages, may be controlled such that latch-up and cell upsets may be reduced or minimized.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.